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FAN5230
System Electronics Regulator for Mobile PCs
Features
* * * * * * * * * * * * * * * * * * * * * 5.4V to 24V input voltage range Five regulated outputs: 5V @ 5A (PWM) 3.3V @ 5A (PWM) 5V @ 50mA Always On (Linear) 3.3V @ 50mA Always On (Linear) 12V/Adjustable @ 120mA Boost (PWM) >96% efficiency Hysteretic mode for light loads PWM mode for normal loads Main regulators switch out of phase 300kHz fixed frequency switching RDS(ON) current sense over-current Reduced BOM; Max. efficiency Optional current sense resistor for precision over-current detect Power Good signal for all voltages Input under-voltage lock-out (UVLO) Thermal shutdown ACPI compliant 24-pin QSOP 2nd source by Intersil (IPM6220)
Description
The FAN5230 is a high efficiency and high precision multiple-output voltage regulator for notebook PC and other similar battery-powered applications. It integrates three pulse-width modulated (PWM) switching regulator controllers and two linear regulators to convert 5.4V-to-24V notebook battery power into the voltage used by the circuitry that surrounds the microprocessor in these systems. The two primary PWM controllers in the FAN5230 use synchronous-mode rectification to provide 3.3V and 5V at over 5A each. They switch out-of-phase to minimize input ripple-current. Utilization of both input and output voltage feedback in a current-mode control allows for fast and stable loop response over a wide range of input and output variations. PWM control in normal operation and hysteretic control under light load provides efficiency of greater than 95% over a wide range of input and output variations. The third PWM controller generates 12V at 120mA. A proprietary technology is used for accurate [ 1%] sensing of output current using the RDS(ON) of the external MOSFETs, eliminating external current sense resistors which saves board space and reduces BOM cost. Two integrated linear regulators provide stand-by ALWAYSON power at 3.3V and 5V for light (50mA) loads. Additional FAN5230 features include over-voltage, under-voltage, and over-current monitors and thermal shutdow protection. A single Power-Good signal is issued when soft start is completed and all outputs are within 10% of their settings.
Applications
* Notebook PCs * Web tablets * Battery-powered instruments
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FAN5230
Typical Application
Vin = 5.4-24V
FAN5230 1 VIN 3.3V-ALWAYS@50mA 5V-ALWAYS 2 3.3 ALW 3 CPUMP3.3 4 HSD3.3 3.3V @ 5A + 5 SW3.3 5V-ALWAYS@ 50mA 6 5V-ALW 7 LSD3.3 8 GND3.3 9 ISEN3.3 10 VFB3.3 SDN3.3 PGOOD 11 SDN3.3 12 PGOOD LSD5 20 GND5 19 VFB5 18 SDN5 17 SW12 16 VFB12 15 SGND 14 SDWN 13 SDWN VFB12 SDN5 12V @ 120mA + CPUMP5 24 HSD5 23 SW5 22 ISEN5 21 5V-ALWAYS 5V @ 5A +
Pin Assignments
Top View
VIN 3.3V-ALWAYS CPUMP3.3 HSD3.3 SW3.3 5V-ALWAYS LSD3.3 GND3.3 ISEN3.3 VFB3.3 SDN3.3 PGOOD 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CPUMP5 HSD5 SW5 ISEN5 LSD5 GND5 VFB5 SDN5 SW12 VFB12 SGND SDWN
Pin Description
Pin Name VIN 3.3V-ALWAYS CPUMP3.3 HSD3.3 SW3.3 5V-ALWAYS Pin Number Pin Function Description 1 2 3 4 5 6 Input power. 3.3V Always on linear regulator. Load current on pins 2 and 6 must not exceed 50mA total. This pin should be decoupled to ground with a 10F capacitor. Charge Pump 3.3V. High side Gate drive voltage for 3.3V. This pin is to be connected to SW3.3 through a 100nF cap. and to 5V-ALWAYS through a diode High-side gate driver for 3.3V. Connect this pin directly to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be < 1". High side FET Source and Low Side FET Drain Switching Node. Switching node for 3.3V. 5V Always on linear regulator output. The sum of the load currents on pins 2 and 6 must not exceed 50mA total. This pin should be decoupled to ground with a 10F capacitor.
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FAN5230
Pin Description (Continued)
Pin Name LSD3.3 GND3.3 ISEN3.3 VFB3.3 SDN3.3 PGOOD SDWN Pin Number Pin Function Description 7 8 9 10 11 12 13 Low-side gate driver for 3.3V. Connect this pin directly to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be < 1". Ground for 3.3V MOSFET. Current sense for 3.3V. This pin should be connected to the Drain of the bottom Mosfet with an appropriate resistor and an RC filter. See Application Section. Voltage feedback for 3.3V. Soft Start and ON/OFF for 3.3V. OFF=GND. ON=open with SDWN=High. Use open collector device for control. Power Good Flag. An open collector output that will be logic low if any output voltage is not above 89% of the nominal output voltage. Master Shutdown. Shutdown for all power. Off when low. When high 5V/3.3V-ALWAYS are ON while 5V/3.3V-Main are ready to turn on if SDN5, SDN3.3 go open. Signal ground. Voltage feedback for 12V. FET driver for 12V Boost. Enable/Soft Start for 5V and 12V. Soft start and ON/OFF for 5V & 12V. OFF=Grounded. ON=open with SDWN=High. Voltage feedback for 5V. Ground for 5V MOSFET. Low side FET driver for 5V. Connect this pin directly to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be < 1". Current Sense for 5V. This pin should be connected to the drain of the bottom Mosfet using appropriate resistor and RC filter. See Application Section. High Side Driver Source and Low Side Driver Drain Switching Node. Switching node for 5V. High side FET driver for 5V. Connect this pin directly to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be < 1". Charge Pump 5V. High side Gate drive voltage for 5V. High side Gate drive voltage for 5V. This pin is to be connected to SW5 through a 100nF cap. and to 5V-ALWAYS through a diode.
SGND VFB12 SW12 SDN5 VFB5 GND5 LSD5 ISEN5 SW5 HSD5 CPUMP5
14 15 16 17 18 19 20 21 22 23 24
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FAN5230
Absolute Maximum Ratings1
Parameter VIN SW, ISEN Pins,SDWN Pin CPUMP, HSD Pins SDN, VFB, V_always pins CPUMP to SW pins, and all other pins Conditions Min. -0.3 -0.3 -0.3 -0.3 -0.3 Typ. Max. 27 27 33 6.5 6.5 Units V V V V V
The sum of the load currents on pins 2 and 6 must not exceed 60mA total
Note: 1. Stresses beyond "Absolute Maximum Ratings" may cause permanent device damage. Continuous exposure to absolute maximum rating conditions may affect device reliability. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification is not implied.
Recommended Operating Conditions
Input Voltage, VIN Ambient Temperature, TA +5.4V to 24V -20C to 85C
Thermal Information
Thermal Resistance, RTHJA Thermal Resistance, RTHJC Maximum Junction Temperature Storage Temperature Range Maximum Lead Temperature, Soldering 10 Sec 88C/W 28.5C/W 150C -65C to 150C 300C
ELECTRICAL SPECIFICATIONS Operating Conditions
Recommended Operating Conditions Unless Noted Refers to Block Diagrams Parameter Supply VIN Input Supply Voltage Input Quiescent Current (DC loading only) Note 1 H/LSD Open Stand-by Shut-down Input UVLO Threshold 5V and 3.3V Main Regulators Output Voltage Precision Oscillator Frequency, fosc HSD On-Resistance, pull up HSD On Resistance pull down LSD On-Resistance, pull up LSD On Resistance pull down 0.1 to 5.5A, 5.4 to 24V -2 255 300 7 4 6 5 +2 345 12 10 9 8 % kHz Rising Vbat hysteresis 4.3 5.4 1.4 300 <1 4.7 100 24 3 400 5 5.1 V mA A A V mV Conditions Min. Typ. Max. Units
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FAN5230
Operating Conditions (Continued)
Recommended Operating Conditions Unless Noted Refers to Block Diagrams Parameter HSD On Output, VCPUMP-VGS HSD Off Output, VGS LSD On Output, V5V-Always-VGS LSD Off Output, VGS Ramp Amplitude, pk-pk Ramp Offset Ramp Gain from VIN Error Amplifier GBW Current Limit Threshold Over Voltage Threshold Under Voltage Threshold SDN/SS Full On Voltage Min. SDN/SS Full Off Voltage Max. Max Duty Cycle Min PWM Time VFB3.3 Input Leakage Current 12V Regulator Output Voltage Precision VFB12 VFB12 Input Current Oscillator Frequency (fosc/3) Gate Drive On-Resistance 12V Regulator (Continued) On Output, V5V-Always-VGS Off Output, VGS Ramp Amplitude, pk-pk Error Amplifier GBW Under Voltage Shut Down Over Voltage Shut Down Min Duty Cycle Max Duty Cycle 5V and 3.3V Always Bypass Switch rdson Linear Regulator Accuracy Rated Output Current Over-current Limit Under-voltage Threshold Reference Internal Reference Accuracy 0-70C -1 1 % 5.6 to 24V, 0 to 50mA, 5V Main On or Off I3.3 + I5 2s delay 2s delay -3.3 0 100 70 180 75 80 1.3 1.5 2 50 % mA mA % (By design) 2s delay Measured at VFB12 0 32 33 34 70 I = 10A I = 10A 2 1 76 115 80 100 100 mV mV V MHz %VO %VO % % High or Low Note 2 85 V_5 =4.9 to 5.1V and Io=0 to 150mA -2 2.472 100 100 6 200 115 12 +2 % V nA kHz 40 94 200 55 70 R2, R8 = 1K 2s delay 2s delay (End of Soft Start) 90 110 70 4.2 800 Conditions I = 10A I = 10A I = 10A I = 10A VIN = 16V 2 0.5 125 3 135 115 75 180 120 80 Min. Typ. Max. 100 100 100 100 Units mV mV mV mV V V mV/V MHz A %VO %VO V mV % nsec A
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FAN5230
Operating Conditions (Continued)
Recommended Operating Conditions Unless Noted Refers to Block Diagrams Parameter Control Functions SDWN Off Voltage Max. SDWN On Voltage Min. Over-temperature Shutdown, tj Over-temperature Hysteresis PGOOD Threshold PGOOD Sink Current PGOOD leakage +5V Analog Softstart +3.3V Analog Softstart Soft Start Current PGOOD Min Pulse Width Note 2 5 Css=100nF Css=100nF 65 65 5 10 PWM Buck Converters -14 -4 1 3 150 25 -11 -8.5 800 mV V C C %VO1 mA A msec msec A s Conditions Min. Typ. Max. Units
Notes 1. The minimum input voltage does not include voltage drop in the source supply due to source resistance. It is operating voltage for static load conditions. To get acceptable load transient performance, the input voltage required will be much higher, in the 7.5 to 8.5 volt range or even higher depending on the severity of dynamic load, source impedance and input and output capacitance and inductor values. The user should thoroughly test the performance at minimum input voltage using intended component values and transient loading. 2. Min/Max specifications are guaranteed by design.
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5V VIN CPUMP HSD CLK HYST PHASE L1 ADAPTIVE GATE CONTROL ISEN VCC LSD PGND CL VOUT GATE LOGIC PWM PWM/HYST LO HI VFB
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+ - -
VCC Q D CLK Q CLR L
SET
+ REF OC DETECT
-
HYSTERIC COMPARATOR +
VFB -
SUM
PWM LATCH - + PWM
+ - LSD RAMP LSD - + CURRENT SENSE AMP VREF ERROR AMP
+
DUTY CYCLE CLAMP
ISEN
MODE CONTROL
FAN5230 5V/3.3V Switcher
Figure 1. FAN5230 5V/3.3V Internal Block Diagram of PWM/PFM Loops.
FAN5230
7
FAN5230
CK:3 CK :3 Ve Ramp PWM VREF=2.5V R Ramp 16R Vout - - + VFB12 Ve CLK:3 + PWM R S
FAN5230 12V Converter +5
CLK:3 (30%DC, 100kHz)
SW12
V out
Q
Q
DISABLE
Figure 2. FAN5230 12V Internal Block Diagram
VIN FAN5230 5V/3.3V-ALWAYS LDO
3.3V ALWAYS
LDO
5V ALWAYS
VFB5
Figure 3. FAN5230 5V/3.3V--ALWAYS Internal Block Diagram
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FAN5230
Functional Description
The FAN5230 is a high efficiency and high precision DC/DC controller for notebook and other portable applications. It provides all of the voltages necessary for system electronics: 5V, 3.3V, 12V, and both 3.3V-ALWAYS and 5V-ALWAYS. Utilization of both input and output voltage feedback in a current-mode control allows for fast loop response over a wide range of input and output variations. Current sense based on MOSFET RDS,on gives maximum efficiency, while also permitting the use of a sense resistor for high accuracy.
(HSD and LSD off). This is the likely scenario in the case of a "soft" short. If the short is "hard" it will instantly trigger the under-voltage protection which again will latch the regulator off (HSD and LSD off) after a 2s delay. Selection of a current-limit set resistor must include the tolerance of the current-limit trip point, the MOSFET on resistance and temperature coefficient, and the ripple current, in addition to the maximum output current. Example: Maximum DC output current on the 5V is 5A, the MOSFET RDS,on is 17m, and the inductor is 5H at a current of 5A. Because of the low RDS,on, the low-side MOSFET will have a maximum temperature (ambient + self-heating) of only 75C, at which its RDS,on increases to 20m. Peak current is DC output current plus peak ripple current:
3.3V and 5V Architecture
The 3.3V and 5V switching regulator outputs of the FAN5230 are generated from the unregulated input voltage using synchronous buck converters. Both high side and lowside MOSFETs are N-channel. The 3.3V and 5V switchers have pins for current sensing and for setting of output over-current threshold using MOSFET RDS,on. Each converter has a pin for voltage-sense feedback, a pin that shuts down the converter, and a pin for generating the boost voltage to drive the high-side MOSFET. If the 5V switcher is not used, connect SDN5 (pin 17) to SGND (pin 14). If the 3.3V switcher is not used, connect SDN3.3 (pin 11) to SGND (pin 14). The following discussion of the FAN5230 design will be done with reference to Figures 1 through 4, showing the internal block diagram of the IC.
Ipk Idc +
TV0 2L
= 5A +
4sec * 5V = 7A 2 * 5H
where T is the maximum period, VO is output voltage, and L is the inductance. This current generates a voltage on the low-side MOSFET of 7A * 20m = 140mV. The current limit threshold is typically 150mV (worst-case 135mV) with R2 = 1K, and so this value is suitable. R2 could be increased a further 10% if additional noise margin is deemed necessary.
Precision Current Limit
Precision current limiting can be achieved by placing a discrete sense resistor between the source of the low-side MOSFET and ground. In this case, current limit accuracy is set by the tolerance of the IC, +10%.
HSD SW LSD ISEN
3.3V and 5V PWM Current Sensing
Peak current sensing is done on the low side driver because of the very low duty-cycle on the high side MOSFET. The current is sampled 50ns after turn on and the value is held for current feedback and over-current limit.
3.3V and 5V PWM Loop Compensation
The 3.3V and 5V control loops of the FAN5230 function as voltage mode with current feedback for stability. They each have an independent voltage feedback pin, as shown in Figure 1. They use voltage feed-forward to guarantee loop rejection of input voltage variation: that is to say that the PWM (pulse width modulation) ramp amplitude is varied as a function of the input voltage. Compensation of the control loops is done entirely internally using current-mode feedback compensation. This scheme allows the bandwidth and phase margin to be almost independent of output capacitance and ESR.
GND
3.3V and 5V PWM Current Limit
The 3.3V and 5V converters each sense the voltage across their own low-side MOSFET to determine whether to enter current limit. If an output current in excess of the current limit threshold is measured then the converter enters a pulse skipping mode where Iout is equal to the over-current (OC) set limit. After 8 clock cycles then the regulator is latched off
Figure 4. Using a Precision Current Sense Resistor
Shutdown (SDWN)
The SDWN pin turns off all 5 converters (+5V, +3.3V, and +12V, 5V/3.3V-ALWAYS) and puts the FAN5230 into a lowpower mode (Shutdown mode).
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FAN5230
This mode of operation implies the use of a push button switch between SDWN and Vin. Pushing the button allows (for the duration of the contact) to power the 3.3V-ALWAYS and 5V-ALWAYS long enough for the uC to power up and in turn latch the SDWN pin high. Once the SDWN is high then the ALWAYS voltages are enabled to go high if the respective SDN3.3 and SDN5 go high.
As the load current becomes very light, the FAN5230 begins pulse skipping, but remains synchronized with the clock. See next section for low side drive management.
Low Side Driver Forcing in Light Load
During light load operation, the Low Side Driver (LSD) is traditionally turned permanently OFF to avoid current inversion in the inductor and associated efficiency losses. At the same time the low side driver also needs to be turned ON in order to a) measure current (current is sensed on the low side driver) and b) assure proper operation of the charge pump, especially under low current and low input voltage conditions. In order to accomplish all the above, when the circuit enters hysteretic operation the LSD is kept "ON" to re-circulate positive and decaying currents (corresponding to negative drops across low side driver Rdson) and turned off as soon as current crosses zero (corresponding to drop across Rdson becoming positive). This way the low side driver is utilized in "partial duty" or as "active zero drop diode" (compared to classic light load operation in which the LSD is turned permanently OFF) allowing more functionality without loss in efficiency.
MAIN 3.3V and 5V Softstart, Sequencing and Stand-by
Softstart of the 3.3V and 5V converters is accomplished by means of an external capacitor between pins SDN3.3 (SDN5) and ground. The 3.3V (5V) main converter is turned ON if SDWN and SDN3.3 (SDN5) are both high and is turned off if either SDWN or SDN3.3 (SDN5) is low. Stand-by mode is defined as the condition by which V-Mains are OFF and V-ALWAYS are ON (SDWN=1 and SDN3.3=SDN5=0).
ALWAYS mode of Operation
If it is desired that 5V-ALWAYS and 3.3V-ALWAYS are always ON then the SDWN pin must be connected to Vin permanently. This way the two ALWAYS regulators come up as soon as there is power while the state of the Main regulators can be controlled via the SDN5 and SDN3.3 pins.
3.3V Voltage Adjustment
The output voltage of the 3.3V converter can be increased by as much as 10% by inserting a resistor divider in the feedback line. The feedback pin impedance is about 66K. Thus, for example, to increase the output of the 3.3V converter by 10%, use a 2.21K/33.2K divider. Note that the output of the 5V regulator cannot be adjusted. The feedback line of the 5V regulator is used internally as a 5V supply and, therefore, cannot tolerate any impedance in series with it.
Sequencing Table
SDN5 X 0 1 0 1 3V&5V SDN3.3 SDWN ALWAYS X 0 0 0 1 1 0 1 1 1 1 1 1 1 1 5V MAIN 0 0 1 0 1 3.3V MAIN 0 0 0 1 1
3.3V and 5V Main Overvoltage Protection (Soft Crowbar)
When the output voltage of the 3.3V (or the 5V) converter exceeds approximately 115% of nominal, the converter enters the over-voltage (OV) protection mode, with the goal of protecting the load from damage. During operation, severe load dump or a short of an upper MOSFET could cause the output voltage to increase significantly over normal operation range without circuit protection. When the output exceeds the overvoltage threshold, the over-voltage comparator forces the lower gate driver high and turns the lower MOSFET on. This will pull down the output voltage and eventually may blow the battery fuse. As soon as output voltage drops below the threshold, OVP comparator is disengaged. The OVP scheme also provides a soft crowbar function (bang-bang control followed by blow of the fuse) which helps to tackle severe load transients but does not invert output voltage when activated--a common problem for OVP schemes with a latch. The prevention of output inversion eliminates the need for a Schottky diode across the load.
3.3V and 5V Light Load Mode
The 3.3V and 5V converters are synchronous bucks, and can operate in two quadrants, this means that the ripple current is constant and independent of the load current. At light loads, this ripple current translates into poor efficiency, since it causes circulating current losses in the MOSFETs. To optimize the efficiency at light loads, then, the FAN5230 switches from normal operation to a special light load mode after an 8 clock pulse delay. This prevents false triggering when the voltage across the on-state low-side MOSFET goes positive. Vice-versa when this voltage becomes negative the FAN5230 switches back to PWM operation. The current threshold for switch to and from light load is therefore: Ith = Iripplepeak In light load mode, the FAN5230 switches from PWM (pulse width modulation) to PFM (pulse frequency modulation), which reduces the gate drive current.
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FAN5230
3.3V and 5V Under-voltage Protection
When the output voltage of either the 3.3V or 5V falls below 75% of the nominal value, both converters, go into under-voltage (UV) protection, after a 2sec delay. In undervoltage protection, the high and low side MOSFETs are turned off. Once under-voltage protection is triggered, it remains on until power is recycled or the SDWN pin is reset.
5V/3.3V-ALWAYS Operation
The 5V-ALWAYS supply is generated from either the on-chip linear regulator or through an internal switch from the VFB pin of the 5V switching supply. The 5V-ALWAYS supply should be decoupled to ground with a 10F capacitor. When the 5V switching supply is off, or if its output voltage is not within tolerance, the 5V-ALWAYS switch is open, and the linear regulator is on. When the 5V switching supply is running and has an output voltage within specification, the linear regulator is off, and the switch is on. The switch has sufficiently low resistance that at maximum current draw on the 5V-ALWAYS supply, the output voltage is regulated within specifications. The 3.3V-ALWAYS is generated from a linear regulator attached internally to the 5V-ALWAYS. The 3.3V-ALWAYS supply should be decoupled to ground with a 10F capacitor. The purpose of the two ALWAYS supplies (combined current is specified to never exceed 50mA) is to provide power to the system micro-controller (8051 class) as well as other IC's needing a stand-by power. The micro-controller as well as the other IC's could be operated from either 5V or 3.3V ALWAYS, so the FAN5230 provides both.
12V Architecture
The 12V converter is a traditional non-isolated fly-back (also known as a "boost" converter). The converter's input voltage is the +5V switcher output, so that +12V can only be present if +5V is present. Also, if the external MOSFET is off, the output of the +12V converter is +5V, not zero. This in turn will provide non-zero output for the 12V regulator. For complete turn-off of the 12V regulator an external P-channel MOSFET or an LDO regulator with on/off control may be used. If an LDO is used for 12V then the boost converter should be set to 13.2V using the external resistor divider network. If the 12V "boost" converter is not used, connect VFB12 (pin 15) to 5V-ALWAYS (pin 6).
12V Loop Compensation
The 12V converter should be run in discontinuous conduction mode. In this mode, the converter will be stable if a capacitor with suitable ESR value is selected. A 68uF tantalum with 500mA ripple current rating and 95m is recommended here.
5V/3.3V-ALWAYS Protections
The two internal linear regulators are current limited and under-voltage protected. Once protection is triggered all outputs are turned off until power is cycled or the SDWN is reset.
12V Protection
The 12V converter is protected against overvoltage. If the 12V feedback is more than 10-15% above the nominal set voltage, a comparator forces the MOSFET off until the voltage falls below the comparator threshold. The 12V converter is also protected against over-current. If a short circuit pulls the output below 9V, all of the switching converters go into UV protection, after a 2s delay. In UV protection, all MOSFETs are turned off. Once UV protection is triggered, it remains on until the input power is recycled or the SDWN is reset.
Power good
Power good is asserted when both PWM Buck converters are above specified threshold. No other regulators are monitored by Power good. When PGOOD goes low it will stay low for at least 10sec (Tw). See fig. 5.
Vmain Vth
12V Softstart and Sequencing
The 12V output is started at the same time as the 5V output. The softly rising 5V output automatically generates a softly rising 12V output. The duty cycle of the 12V PWM is limited to prevent excessive current draw. The 12V supply must build up a voltage higher than the UVLO limit (9V) by the time the 5V is above its UVLO (3.75V) in order to avoid triggering of UV protection during soft start.
Tw
t
PGOOD
t
Figure 5. PGOOD Timing Diagram
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FAN5230
Error Amplifier output voltage clamp
During a load transient the error amplifier voltage is allowed full swing. After two clock cycles, if the amplifier is still out of range the voltage and consequently the duty cycle (DC) is clamped. The DC clamp automatically limits the build up of over-currents during abnormal conditions, including short circuits:
VFB=0.5V+Vo/8 - VREF EA + VRAMP =0.5V+Vin/8 + -
Input UVLO
If the input voltage falls below the UVLO threshold, the FAN5230 turns itself off and stays off as long as Input voltage is below threshold.
IC Protections Table
HSD Buck OC/UV (Bucks) OC/UV (LDO) OV (Buck)* LSD Buck LDO
ON
LSD Boost
OFF-LATCH
OFF-LATCH OFF-LATCH
"
"
OFF-LATCH
"
OFF ON OFF OFF
Vclamp=0.5V+ +Vo/8 +/-0.2V
SOFT CROWBAR ON OFF OFF
ON ON OFF OFF ON ON
ON OFF OFF OFF OFF-LATCH 33% DC
0.4V
OV (Boost) SDWN=0 OT
-
2 Cycles Counter
Figure 6. Duty-Cycle Clamp
+
UV (Boost) OC (Boost)
OFF-LATCH OFF-LATCH ON ON
* Only the converter in Over-Voltage goes in SOFT CROWBAR mode.
Thermal shutdown
If the die temperature of the FAN5230 exceeds safe limits, the IC shuts itself off. When the over-temperature (OT) event ends, the IC comes back to normal operation. There is a 25C thermal hysteresis between shutdown and start up.
Generic Mobile System Block Diagram
Vin=5.6 to 24V
5V SDN5 3.3V SDN3.3 RC5230 C 8051 5V-Always PGOOD 3.3V-Always C PGOOD EN RC5231 1.5V CPU 2.5V P Clock CPU PGOOD Vcpu
SDWN SDWN
P CODE EXECUTION
RESET LOGIC
Figure 7. System Block Diagram
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FAN5230
Notebook Application Circuit
5.4-24V C1 Pin 6 C2 3.3V@50mA 5V@50mA 3.3V@5A C10 C11 + C12, C13 D1 Q2 R2 SDN3.3 D5 L1 C5 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q3 R3 Q4 L3 D4 C6 D2 L2 C7 C8 + 5V@5A
Q1
U1 FAN5230
SDN5
D3 R6 Q5 C4 C9 R4 R5
12V@120mA
C3
+5V R1
SDWN
PGOOD
Figure 8. FAN5230 Notebook Application Circuit
Table 1. FAN5230 Application Bill of Materials
Reference C1 Manufacturer, Part # SANYO 25SP33M Any KEMET T510X337(1)010AS AVXTPSA106010#1800 AVX TPSV68*025R0095 Any Any Any Any Fairchild SS22 Fairchild MBR0520L Any Any Fairchild FDS6690A Fairchild NDC631N Fairchild FAN5230 Quantity 1 Description 33F, 25V Comments OSCON, Irms = 3A, 19V adapter. Ceramic Tantalum, ESR=35m Tantalum, ESR=1.8 Tantalum, Irms = 0.5A
C2-6 C7-8 C12-13 C10-11 C9 R1 R2, R3 R4, R5 R6 D1-3 D4-5 L1-2 L3 Q1-4 Q5 U1
5 2 2 2 1 1 2 1 1 3 2 2 1 4 1 1
100nF, 50V 330F, 10V 10F, 10V 68F, 25V, ESR=95m 10K, 1% 1K, 1% 380K, 100K 10 2A, 40V Schottky 500mA, 20V Schottky 6.4H, 5A 5.6H, 2A 30V N-channel MOSFET 20V N-channel MOSFET SER Controller
1%
R < 25m R = 17m R = 60m
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FAN5230
MOSFET Selection
The notebook application circuit shown in Figure 1 is designed to run with an input voltage operating range of 5.4-24V. This wide input range helps determine the selection of the MOSFETs for the 3.3V and 5V converters, since the high-side MOSFET is on (Vout / Vin) of the time, and the low-side MOSFET 1 - (Vout / Vin) of the time. The maxima and minima are tabulated in Table 2:
3.3V and 5V Schottky Selection
The maximum current at which the converters operate in PFM mode determines selection of a Schottky. In the application shown in Figure 8, since the transition can occur at a current as high as 28mV * (17.5K / 10K) / 35m = 1.4A, the diode (with 24V input) will be conducting 86% of the period (from Table 2). It thus has an average current of 1.4A * 0.86 = 1.2A, which requires a Schottky current rating >1A.
Table 2. MOSFET Duty Cycles High-side FET
Vin Vout 3.3V 5V 5.4V .61 .43 24V .14 .21
3.3V and 5V Inductor Selection
See Table 1.
3.3V and 5V Output Cap Selection
See Table 1.
12V Component Selection
Calculation of the inductor, diode and output capacitor for the +12V output fly-back is complex, depending on output power and efficiency. See Applications Bulletin AB-19 for an Excel spreadsheet calculation tool. See Table 1 also.
Low-side FET
Vin Vout 3.3V 5V 5.4V .34 .07 24V .86 .79
Input Capacitor Selection
Input capacitor selection is determined by ripple current rating. With two converters operating in parallel at differing duty cycles, calculation of input ripple current is complex; see Applications Bulletin AB-19 for an Excel spreadsheet calculation tool.
All four MOSFETs have maximum duty cycles greater than 50%. Thus, it is necessary to size all four approximately the same.
Efficiency
100 90 80 70 Efficiency (%) 60 50 40 30 20 10 0 1 10 100 Load Current mA PWM Hyst 1,000 10,000
14
REV. 2.8.5 10/17/01
FAN5230
Mechanical Dimensions
QSOP 24-Lead
Symbol A A1 A2 b c D E e H L N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .006 inch (0.15mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 5 2, 4 2 5. "b" and "c" dimensions include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
0.0532 0.0668 0.0040 0.0098 0.054 0.062 0.008 0.012 0.0075 0.0098 0.337 0.344 0.150 0.157 0.025 BSC 0.228 0.016 24 0 -- 8 .004 0.244 0.050
1.35 1.75 0.1 0.25 1.37 1.57 0.20 0.30 0.19 0.25 8.55 8.74 3.81 3.99 0.635 BSC 5.79 0.40 24 0 -- 8 0.10 6.20 1.27
3 6
D
E
H
A
A2 B e
A1 SEATING PLANE -C- LEAD COPLANARITY ccc C L
C
REV. 2.8.5 10/17/01
15
FAN5230
Ordering Information
Product Number FAN5230QSC Package 24 Lead QSOP
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
10/17/01 0.0m 002 Stock#DS30005230 2001 Fairchild Semiconductor Corporation

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